In general, networks and computers operate in different manners. Networks operate by transferring data in streams and/or packets. Streams may be bit-sized, byte-sized, or otherwise broken down. Packets may be of relatively large size, such as 64, 512, or more bytes each. Computers operate by processing data, typically in well-defined small sizes, such as bytes (8 bits), words (16 bits), double words (32 bits) and so on. At the interface between a computer and a network, a translation or reorganization of data may be necessary. This may include reorganizing data from a series of packets into a format useful to a processor. In particular, this may include taking data bits of a series of bytes and reorganizing them into a form including only data bits. A similar problem may occur at a byte-level, wherein some bytes of a group of bytes are data bytes, and other bytes are effectively control bytes which need to be parsed out of data.
FIG. 1A illustrates in block diagram form an embodiment of a conventional circuit for aligning and storing portions of data. FIG. 1B illustrates in block diagram form operation of the embodiment of FIG. 1A. This circuit may be used to align and properly store data parsed from a stream of data and control bits. Input register 110 receives data in an unpacked form, up to p bytes wide. Aligner 120 receives the data from input register 110, and lines the bits up at the beginning of the register. Based on data already in memory 150 of memory block 140, Barrel Shifter 130 shifts the bits from aligner 120 to a desired location. For example, if the old data already in memory storage location 155 takes up part of the storage location, a tail pointer 135 will point to the first bit available in memory storage location 155. Tail pointer 135 may be used by barrel shifter 130 to determine where to shift the data. The data may then be written to memory storage location 155 in a bit-wise fashion, such that memory storage location 155 contains both the old data and the new data received in input register 110. Note that memory block 140 is used to store data for n (more than 1) channels of data, and may be implemented such that it contains one memory 150 for each channel, for example.
FIG. 1C illustrates in flow diagram form operation of the embodiment of FIG. 1A. At block 175, data is received in unpacked form, such as in input register 110. At block 178, pointer values, such as tail pointer 135, are calculated, determining where data is already stored in the appropriate memory storage location. At block 180, the new data received is aligned, such as in aligner 120. This alignment shifts the new data to the 0 bit of the aligner 120, and allows the barrel shifter 130 to operate on the data properly. At block 185, the new data is barrel shifted (such as in barrel shifter 130 for example), based on the tail pointer 135. At block 188, a write enable mask is calculated, such that only the new data of the barrel shifter 130 will be written. At block 190, using the write enable mask, data from barrel shifter 130 is written to a memory storage location such as memory storage location 155.
This approach suffers from requirements of increasing logic for increasing bus widths. Whereas a 4 bit barrel shifter may require n gates, an 8 bit barrel shifter may require 4n gates, and a 16 bit barrel shifter may require 16n gates for implementation. Thus, as bus widths grow, this approach requires exponential growth in logic.